Matthew C. Dewey
1295 West 12th Avenue
Broomfield, CO 80020
(303) 439-7431

Experience:

Dynatek/Retrieve Inc. March 1996 - Present

Product is a file processor based on a file system from Programmed Logic and using the VxWorks RTOS. The product uses SCSI or Fibre Channel as the communication channel to a Solaris or NT host. Code is implemented in C++ and C for an embedded PC platform.

Designed and developed a C++ framework for embedded systems including; boot and shutdown, event logging and reporting, configuration persistence, debug user interface, cron.

Significant contributor to the protocol architecture including SCSI mapped files, command regions and messaging. The protocol is transported on unmodified SCSI drivers between the host and the file processors. It supports an RPC type mechanism with commands taking unspecified amounts of time without triggering driver command time-outs.

Designed and developed subsystems specific to this product including;

·         Pseudo-NVRAM - emulates an NVRAM by hooking all exit and crash paths and storing the pseudo-NVRAM contents to disk before the system goes completely down.

·         Storage Manager - automatically handles the configuration management of the disk storage. Allows automatic storage growth when new devices are added.

·         Version Manager - handles software upgrade and allows 5 previous versions of software to be kept on board to support backing out a defective upgrade.

·         UPS - monitors the system UPS, reports and takes actions as required.

·         UUII - Web based configuration and debug interface to the file processor, allows selected internal variables to be viewed and modified. Coders are required to only declare the variable as part of the interface and all other handling is automatic.

·         Bypass - Allows the file processor to behave as a plain old disk for debugging the interface and to fake out Solaris and NT disk labeling behavior.

·         Configuration Manager - Archives current system configuration to back end storage to allow the file processor to be replaced without loss of user data.

·         Debug Tools - Parallel Port communication to another PC running DOS or NT to allow real-time information to be logged. Hooking of Pentium debug registers such as rdtsc to allow precise code timing, and model specific registers to get exact instruction and bus cycle counts for code profiling. Interface to the PC speaker. Hooking of page faults and other interrupts. Low-level writer to the IDE drive to support pseudo-NVRAM and coredumps.

Array Technology/EMC August 1991-March 1996

Lead Architect for new RAID software. Full Object-Oriented C++ design. Leading 3 other engineers in design and implementation. EMC closed facility before project was complete.

Provided architectural, design and implementation assistance to two other lead engineers for Modarray 2 (follow on releases) and for a 4 controller product.

Lead Software Engineer for the ModArray 2 product. Responsible for leading and scheduling 6 engineers, including maintenance of existing code base (@150,000 lines of C/C++ code), porting to new hardware architecture (3 new ASICS), and additional features.

While acting as project lead, designed and implemented fault tolerant cache software in C++. Provided architectural lead for follow on enhancements to this feature. The cache was developed under simulation on Visual C++ and then ported to the embedded environment. Caching algorithms include; read caching, read ahead, fault tolerant write caching, write coalescing, quick hits (high speed bypass of internal protocols for faster response on both read and write cache hits). Product met or exceeded all RAID 5 performance goals.

Architectural lead on cache recovery algorithms. This software allowed the unwritten data in the cache to be recovered to disk after a controller hardware or software failure.

Implemented inference engine in C++ used in real-time subsystem environmental monitoring. Designed and implemented a language used to write programs for the inference engine using LEX and YACC.

Lead Engineer for the Fault Tolerant Alpine Storage Management System project including: problem manpower assignments for 6 other engineers, system requirements decisions, software configuration control and bug triage.

Designed read ahead algorithms for RAID 5 disk array controller as well as providing identification, analysis and possible solutions for other performance problem areas.

Debugged and supported system configuration validation code for the disk array including system start-up and shutdown code.

Consultant February 1989-May 1993

Delivered completed products from digital system hardware design through implementation to support of the products into production. The products are the Analog and Digital Systems (ADS) SC6 and CP6 whole house stereo.

Designed the digital hardware for a microprocessor based system which, when coupled with the customers analog design, provides six stereo audio preamplifiers in a single package.

Designed and implemented the software for the above product in ‘C’ and 8031 assembly. This software controls all operations of the product including the following functions:

·         Decoding six infra-red remote control inputs simultaneously in real-time.

·         A token passing bus used to communicate between boxes and control panels to allow control of any room from any other room. The token passing bus also supports downloading the software from the system controller to the control panels.

·         LCD display and keypad scanning on the control panels. Also a port of the token bus interface to send commands to the system controller.

Xylogics Inc. September 1986-July 1991

Evaluated feasibility and cost of various architectures for several proposed products including a 2 channel SCSI-2 product capable of supporting 1000 IOs per second. Also responsible for performance analysis and simulation of Buffered IPI-2 versus SCSI-2.

Designed and implemented firmware for an IPI-2 intelligent caching disk controller on VMEBUS based UNIX systems (SV6800 and SV7800). This design supports concurrent operation on two 10 Megabyte per second IPI disk drives and a VMEBUS with speeds up to 36 Megabytes per second. Responsibilities included:

·         Working with hardware engineers to design a system capable of meeting performance and cost requirements.

·         Estimating manpower for the completion of the project and assigning tasks for 3 other engineers.

·         Leading 3 other engineers in the implementation of this controller as primary software design engineer.

·         Designing and implementing a multi-tasking real-time executive for use in this and other high performance peripheral controllers on VMEBUS or other open system busses.

·         Developing new algorithms to optimize controller performance in various customer operating systems.

·         Specifying the software requirements for the controller board hardware and the microprocessor interface to four ASIC’s (Buffer Management Chip, IPI disk interface, VME DMA Controller and High Speed FIFO).

Added new features, improved performance and solved customer reported problems on an existing 8031 based Multi-bus QIC-2/floppy/ESDI controller. Work included understanding existing software and hardware and writing new software and debugging existing software for a custom 48 bit wide instruction micro-sequencer.

GTE Communication Systems Division, June 1984-September 1986

Designed and implemented human interface software for High Frequency Data Modem. Responsible for software design and manpower estimates for the software on this project. Lead one other engineer in the implementation of this program. Interfaces were on a 20 character LED display and keypad and militarized terminal (AN-USQ69).

Wrote human interface software for an anti-jam high frequency radio modem controller. Also wrote Built-In-Test software for the controller and modem.

Wrote programs for two tightly coupled Bit-Slice DSP processors in 48 bit horizontal micro-code to perform: Discrete Fourier Transforms, BCH encoder and decoder, convolutional encoder and routines to interface to controller over MIL-STD-1553 bus.

Education:

1984 BS Computer Engineering, Syracuse University. G.P.A 3.4

In House Courses: C++ Programming and Object Oriented Design. Requirements Engineering Workshop, SCSI, the Nuts and Bolts.

Languages:

C++, C, PASCAL, APL, Assembler for Pentium, 68000, 80186, 8031, Z80, 6800, 6502, PDP8, some MIPS R3000 and several custom machines using 48 bit wide horizontal instruction microcode.

Patents Filed

Low Latency Cache Recovery

File Processor Protocol